DMOS devices have a restriction that the maximum gate-to-source voltage (Vgs) allowed is much less than the allowed drain-to-source voltage Vds. Typically, DMOS devices have a maximum allowable Vgs of approximately 5.5 V, although the maximum allowable voltage can vary depending on the manufacturing process used. This means that the gate voltage of the switches must be referenced to the source voltage (midp & midn in FIGS. 3 and 4). The source voltage tracks the external voltage applied to the drain of the DMOS devices via the inherent diode in the DMOS devices. To turn on the PDMOS devices the gate voltage must be a minimum of Vtp lower than midp and a maximum of 5.5 V lower than midp. To turn on the NDMOS devices the gate voltage must be a minimum of Vtn higher than midn and a maximum of 5.5 V higher than midn. This results in the need for a novel drive scheme to turn the Dmos devices on and off.
Another important specification for a switch is that the signal must be passed through the switch with as little distortion as possible (switch flatness/linearity) and as little current as possible should be lost while passing through the switch (minimal leakage).